IEC 62530:2007
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
OVERVIEW
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
COMMENTS
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PRODUCT DETAILS
| Status | Revised |
|---|---|
| Edition | 2007 |
| No. of Pages | 663 |
| ICS Classification | 25.040.01 Industrial automation systems in general |
| Committee | TC 91 |
| Available for Purchase | For sale in Singapore only |
| Adoption | IEC : 0 |