IEC 61523-1:2023
Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
OVERVIEW
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
COMMENTS
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PRODUCT DETAILS
| Status | Current |
|---|---|
| Edition | 2023 |
| No. of Pages | 640 |
| ICS Classification | 35.060 Languages used in information technology 25.040.01 Industrial automation systems in general |
| Committee | TC 91 |
| Available for Purchase | For sale in Singapore only |
| Adoption | IEC : 0 |