IEC 62530:2011
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
OVERVIEW
IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
COMMENTS
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PRODUCT DETAILS
| Status | Withdrawn - 02 Jan 2026 |
|---|---|
| Edition | 2011 |
| No. of Pages | 1251 |
| ICS Classification | 25.040.01 Industrial automation systems in general |
| Committee | TC 91 |
| Available for Purchase | For sale in Singapore only |
| Adoption | IEC |