ISO/IEC 18372:2004
Information technology — RapidIO(TM) interconnect specification
OVERVIEW
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
COMMENTS
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PRODUCT DETAILS
| Status | Current |
|---|---|
| Edition | 2004 |
| No. of Pages | 399 |
| ICS Classification | 35.200 Interface and interconnection equipment |
| Committee | ISO/IEC JTC 1/SC 25 |
| Available for Purchase | For sale in Singapore only |
| Adoption | IEC |